Moore's Law dictates that the number of devices per unit area of an integrated circuit (IC) double with each successive technology node. This simple law drives a decrease in cost and an increase in performance between successive generations of the IC. To support such scaling, a minimum feature size (e.g., gate width, etc.) for the devices within the IC is accordingly decreased. To support such aggressive scaling, new fabrication methods such as double-patterning, self-aligned contact formation, and the like, have been introduced.